`timescale 100ns / 100ps

                       
module tb_impulse_gen
    (   output logic                    clk
        );
//*********************** КОНСТАНТЫ ****************************************************************
    localparam ch_num_lp    = 8;

//*********************** СОЗДАНИЕ И ОПИСАНИЕ ПЕРЕМЕННЫХ *******************************************
    logic                   reset_n;
    
    logic                   start;
    logic [31:0]            sync_imp;
    
    logic [ch_num_lp-1:0]   imp;
    logic [ch_num_lp-1:0]   wre;
    logic [31:0]            data;
    logic [31:0]            addr;

    logic vclamp, vsample, vhsync, vhdata, vlsync, vldata, vrsync, vrdata;
    
//********************** БЛОК НЕПРЕРЫВНЫХ НАЗНАЧЕНИЙ ASSIGN ****************************************
    assign sync_imp  = {23'd0, imp, start};
    assign {vclamp, 
            vsample, 
            vhsync,
            vhdata, 
            vlsync, 
            vldata,
            vrsync, 
            vrdata}   = imp;
//********************** ОПИСАНИЕ ПОДКЛЮЧАЕМЫХ БЛОКОВ ***********************************************
    mod_arbiter_imp_gen
        #(  .ch_num (ch_num_lp)
        )
    mod_arbiter_imp_gen_inst1
        (   .clk        (clk),
        
            .addr       (addr),
            .data       (data),
            .wre        (wre)
        );

    genvar ch;
    generate
        for (ch = 0; ch < ch_num_lp; ch++) begin  : gen_mod_impulse_gen
            mod_impulse_gen_group
            mod_impulse_gen_group_inst
                (   .clk        (clk),
                    .reset_n    (reset_n), 
                    .sync_imp   (sync_imp),
                    .addr       (addr[3:0]),
                    .data       (data),
                    .wre        (wre[ch]),
                    
                    .imp        (imp[ch])
                );
        end
    endgenerate;
  
// ********************* БЛОКИ ИНИЦИАЛИЗАЦИИ *******************************************************
    initial begin
        reset_n = 0;
    #25 reset_n = 1;
    end
    
    initial begin        // CLK
        clk = 0;
        forever #5ns clk = ~clk;
    end
    
    initial begin        // CLK

        // repeat (50) begin
            start = 0;
            #100;
            start = 1;
            #50;
            start = 0;
        // end;
    end    
    
//  ********************* ASSIGN *******************************************************************


// ********************* ПРОЦЕССЫ ******************************************************************

    
endmodule